The present invention relates to a method for manufacturing integrated circuits.
In the manufacture of complementary symmetry metal oxide semiconductor (CMOS) integrated circuits in bulk silicon substrates, it is necessary to form a well of opposite conductivity type to the substrate in order to have a location in which to form complementary transistors. For example, a typical CMOS process utilizes an N type silicon substrate in which a P type well is formed. The P channel transistors are formed in the N type substrate, and the N channel transistors are formed in the P wells. When CMOS integrated circuits are manufactured using either an isoplanar or a local oxidation on silicon (LOCOS) process, a number of manufacturing steps are required for the purpose of forming the well and providing the inter-transistor oxidation regions required by the isoplanar or the LOCOS procedures.
Heretofore, typical isoplanar and LOCOS processes utilized silicon nitride (Si.sub.3 N.sub.4) layers for defining the silicon dioxide layers in etching steps. They also utilized oxidation in a steam ambient at high temperature.
It has been found that high temperature steam oxidation introduces silicon nitride into the silicon surface. The introduction of silicon nitride causes compounds of silicon, nitrogen, and oxygen to be present in the channel region of the transistors formed. Such compounds have been found to cause defects in the gate oxide, resulting in transistors having low breakdown voltages and unstable characteristics. However, there is no easy way to remove such compounds from the silicon surface once they have formed.